RISC(Reduced Instruction Set Computer) designed philosophy aimed at simple but powerful instructions that are executed within one single cycle. The RISC philosophy concentrates on reducing the complexity at Hardware end, other way provide grater flexibility and intelligence at Software end. As a result, RISC philosophy places more demands on the compiler.
CISC(Complex Instruction Set Computer) is a traditional design philosophy, which encourage easy and powerful instructions. CISC relies more on the hardware design to execute an instruction. In turn, the CISC instruction are more complicated.
CISC vs. RISC
Today, the efficient Embedded System Design not only approaches for Cost effectiveness or high Speed. The effective performance with minimal power consumption, becomes an important key factor. ARM core uses a RISC architecture, but it is not a pure RISC architecture. The ARM architecture offer's all the benefits of RISC philosophy, like simplicity, pipeline, etc. ARM core is the raw combination of RSIC and CISC philosophy, which becomes its strength.
Major RISC Philosophy implemented:
1. Instructions:- Reduced number of instruction, which can be executed in single cycle. Each instruction is of fixed length to facilitate the pipeline to fetch next instruction before decoding the current instruction.
2. Pipeline:- Instruction broke and executed parallel using pipelines. Pipeline decode the instruction in advance before execution.
3. Registers:- RISC machine equipped with large number of general purpose addressable register set. All registers can be accessed fast in run time like a local memory.
4. Load-Store Architecture:- The RISC philosophy is also known as Load-Store philosophy. RISC philosophy has separate instructions for load and store the register or external memory. As the registers are accessible by address, programmer can manage loading or storing in software.
Major RISC Philosophy implemented:
1. Instructions:- Reduced number of instruction, which can be executed in single cycle. Each instruction is of fixed length to facilitate the pipeline to fetch next instruction before decoding the current instruction.
2. Pipeline:- Instruction broke and executed parallel using pipelines. Pipeline decode the instruction in advance before execution.
3. Registers:- RISC machine equipped with large number of general purpose addressable register set. All registers can be accessed fast in run time like a local memory.
4. Load-Store Architecture:- The RISC philosophy is also known as Load-Store philosophy. RISC philosophy has separate instructions for load and store the register or external memory. As the registers are accessible by address, programmer can manage loading or storing in software.
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