Introduction to ARM10

The ARM10 family was announced in 1999. ARM10's purpose was to double the performance of its predecessor on the same fabrication, while allowing for further improvements with smaller processes. It extends the ARM9 pipeline to six stages. It also supports an optional vector floating-point(VFP) unit, which adds a seventh stage to the ARM10 pipeline. The VFP significantly increases floating-point performance and is compliant with the IEEE 754.1985 floating-point standard.
ARM10 is the first ARM core to support architecture version 5TE. This is a superset of version 4T, adding BLX (branch-with-link and toggle Thumb/ARM mode), CLZ (count leading zeroes, useful for DSP operations), and BRK (software breakpoint). Production ARM10 processors actually support v5TE, which adds signal processing (saturate-on-overflow) instructions.
The ARM1020E is the first processor to use an ARM10E core. Like the ARM9E, it includes the enhanced E instructions. It has separate 32K D + I caches, optional vector floating-point unit, and an MMU. The ARM1020E also has a dual 64-bit bus interface for increased performance.
ARM1026EJ-S is very similar to the ARM926EJ-S but with both MPU and MMU. This processor has the performance of the ARM10 with the flexibility of an ARM926EJ-S. The ARM1026EJ-S macrocell is a fully synthesizable processor delivering a high level of performance, functionality and flexibility to enable innovative SoC applications. A Jazelle Technology enhanced 32-bit RISC ARM10EJ-S CPU with extensive 64-bit internal bussing is combined with configurable instruction and data caches, configurable tightly coupled memories (TCM), support for parity protection on SRAM arrays, memory management and protection units (MMU and MPU), vector interrupt controller interface, advanced vector floating point support and dual 64/32-bit configurable AMBA AHB system interfaces. The ARM1026EJ-S core implements the ARMv5TEJ instruction set and includes an enhanced 16 x 32-bit multiplier. The ARMv5TEJ instruction set includes 16-bit fixed point DSP instructions to enhance performance of many signal processing algorithms and applications as well as supporting Thumb and Java bytecode execution.

Features:

• 32-bit performance-optimized processor core implementing the ARM, Thumb, DSP, and Java ISAs (v5TEJ)
  - Highly-efficient ARM10EJ-S core achieves 1.35 MIPS/MHz on Dhrystone 2.1 without inlining
  - Extensive 64-bit internal bussing delivers increased bandwidth for applications with large working sets

• Full MMU support for Windows CE, Linux, Palm OS, Symbian OS, and Java OS

• Full MPU support for a broad range of real time operating systems

• Separate instruction and data caches
  - Configurable sizes (4 – 128kB) with 4 way associativity

• Separate instruction and data TCM
  - Configurable sizes (0 – 1MB) and support for wait state insertion

• Parity protection support on SRAM arrays for maximum field reliability

• Dual 64 or 32-bit AMBA AHB bus interfaces

• Direct-attach vector interrupt controller interface for improved interrupt response

• Support for optional vector floating point and embedded trace coprocessors

• EmbeddedICE-RT logic for real-time debug

• Fully-synthesizable and process portable design delivered as RTL

Benefits:

• Flexible, high-performance, low-power core for innovative SoC applications

• Runs all major OSs and existing middleware

• Enables low-cost, single-chip MCU, DSP, and Java solutions

• High-performance hardware Java bytecode execution

• Single development toolkit for reduced development costs and shorter development cycle time

• Synthesizable design allows sourcing from multiple industry-leading silicon vendors

• Excellent real-time debug support for SoC designers via optional ETM10RV macrocell macrocell

• Instruction set can be extended by the use of coprocessors

• ARM-EDA Reference Methodology deliverables significantly reduce the time to generate a specific technology implementation of the core and to generate industry standard views and models.