The structural elements of a Verilog description consist of generic logic gates, library-specific components, and user-defined components connected by wires. In one way, a structural description can be viewed as a simple netlist composed of nets that connect instantiations of gates. However, unlike a netlist, nets in the structural description can be driven by an arbitrary expression that describes the value assigned to the net. A statement that drives an arbitrary expression onto a net is called a continuous assignment. Continuous assignments are convenient links between pure netlist descriptions and functional descriptions. A Verilog structural description can define a range of hierarchical and gate-level constructs, including module definitions, module instantiations, and netlist connections.
The functional elements of a Verilog description consist of function declarations, task statements, and always blocks. These elements describe the function of the circuit but do not describe its physical makeup or layout. One can construct functional descriptions with the Verilog functional constructs. These constructs can appear within functions or always blocks. Functions imply only combinatorial logic; always blocks can imply either combinatorial or sequential logic. Although many Verilog functional constructs appear sequential in nature (for example, for loops and multiple assignments to the same variable), these constructs describe combinatorial logic networks. Other functional constructs imply sequential logic networks. Latches and registers are inferred from these constructs.
Mixing Structural and Functional Descriptions
When a functional description style is used in a design, the combinatorial portions of a design are typically described Verilog functions, always blocks, and assignments.