Verilog

In 1983 Gateway Design Automation released Verilog Hardware Description Language with a Verilog Simulator. In 1989 Cadence bought Gateway Design Automation and split the Verilog Hardware Description Language and the Verilog-XL Simulator. Cadence releases Verilog HDL to public domain. Nearly all ASIC foundries supported Verilog and most used Verilog-XL as a “golden” simulator. This is one that a chip vendor will use to sign-off a chip against, and guarantee that a manufacturing chip will meet the same timing as that of the simulated model. In the year of 1995 Verilog was adopted by IEEE as IEEE standard 1364.

Verilog Features:

• Provides a set of constructs to create concurrent processes to model inherently concurrent digital hardware.

• Supports hierarchical design

• Supports design abstractions

• Supports for various design methodology- Top-down, Bottom-down and Mixed

• Provides a technology independent environment

The following naming conventions apply to Verilog HDL designs:

• Verilog is case sensitive.

• Two slashes “//” are used to begin single line comments. A slash and asterisk “/*” are used to begin a multiple line comment and an asterisk and slash “*/” are used to end a multiple line comment.

• Names can use alphanumeric characters, the underscore “_” character, and the dollar “$” character.

• Names must begin with an alphabetic letter or the underscore.

• Spaces are not allowed within names.

The following is a list of the Verilog reserved keywords:

always	and	assign	Attribute
begin	buf	bufif0	Bufif1
case	casex	casez	Cmos
deassign	default	defparam	Disable
edge	else	end	Endattribute
endcase	endfunction	endmodule	endprimitive
endspecify	Endtable	endtask	event
for	Force	forever	fork
function	Highz0	highz1	if
ifnone	Initial	inout	input
integer	join	large	macromodule
medium	module	Nand	negedge
nmos	nor	Not	notif0
notif1	or	Output	parameter
pmos	posedge	Primitive	pulldown
pullup	pull0	pull1	real
realtime	reg	release	remos
Repeat	rnmos	rpmos	rtran
Rtranif0	rtranif1	scalared	Signed
small	specify	specparam	Strength
strong0	strong1	supply0	Supply1
table	task	time	Tran
tranif0	tranif1	tri	Tri0
tri1	triand	trior	Trireg
unsigned	vectored	wait	Wand
weak0	weak1	while	Wire
wor	xnor	xor