Design Methodology

The shows a typical design process:

The numbers in the above figure are explained below.

• Write a design description in VHDL. This description can be a combination of structural and functional elements.
• Provide VHDL test drivers for the simulator. The drivers supply test vectors for simulation and gather output data.
• Simulate the design by using a VHDL simulator and verify that the description is correct.
• Using Synthesizer, synthesize and optimize the VHDL design descriptions into a gate-level netlist.
• Using your Foundation development system, link the FPGA technology-specific version of the design to the VHDL simulator. The development system includes simulation models and interfaces required for the design flow.
• Simulate the technology-specific version of the design with the VHDL simulator. You can use the original VHDL simulation drivers from Step 2, because module and port definitions are preserved through the translation and optimization processes.
• Compare the output of the gate-level simulation (Step 6) against the output of the original VHDL description simulation (Step 3) to verify that the implementation is correct.