Introduction to ARM11

The ARM11 core was announced in 2003, which based on the ARMv6 instruction set architecture. ARM11 was designed for high performance and power efficient applications. This is achieved using features like, high-performance pipeline and high-bandwidth memory system which, when combined with clock gating throughout, results in a compact and power-efficient microprocessor core. The ARM1136J-S and ARM1136JF-S cores are the first microprocessor cores, implemented on of the ARM11. The cores have an eight-stage pipeline, with two-cycle cache access, to enable high frequency implementation. Both cores feature a flexible, high-performance memory system with configurable instruction and data cache, plus high-speed local memory (TCM) with dedicated DMA to augment the processing of real-time data. Four, high-speed 64-bit system on-chip interconnects ensure ample bandwidth for data and instructions.
The memory management unit (MMU) supports a number of operating systems such as Microsoft, SymbianOS, WindRiver and linux, and includes physically tagged caches - which reduce OS context switch times, and improve processor utilisation by eliminating forced cache flushing by the OS.
The ARM1136J-S core and the ARM1136JF-S core are delivered in a synthesisable format and are designed to work seamlessly with commercially available libraries and RAM compilers, which helps to speed up integration of the cores into system-on-chip (SoC) devices. The 'F' extension added to the ARM1136JF-S core signifies the inclusion of a floating-point coprocessor function that in addition to consumer, wireless applications, and also makes the core highly suitable for automotive applications and the ARM 'E' extensions for DSP acceleration. Both cores include the ARM Jazelle extensions for enhanced Java acceleration.

ARM11 Family Features:

• Powerful ARMv6 instruction set architecture

• ARM Thumb instruction set reduces memory bandwidth and size requirements by up to 35%

• ARM Jazelle technology for efficient embedded Java execution

• ARM DSP extensions

• SIMD (Single Instruction Multiple Data) media processing extensions deliver up to 2x performance for video processing

• ARM TrustZone technology for on-chip security foundation (ARM1176JZ-S and ARM1176JZF-S cores)

• Thumb-2 core technology for enhanced performance, energy efficiency and code density (ARM1156T2-S and ARM1156T2F-S cores)

• Low power consumption:

• 0.6mW/MHz (0.13µm, 1.2V) including cache controllers

• Energy saving power-down modes address static leakage currents in advanced processes

• High performance integer processor

• 8-stage integer pipeline delivers high clock frequency (9 stages for ARM1156T2(F)-S)

• Separate load-store and arithmetic pipelines

• Branch Prediction and Return Stack

• High performance memory system design

• Supports 4-64k cache sizes

• Optional tightly coupled memories with DMA for multi-media applications

• High-performance 64-bit memory system speeds data access for media processing and networking applications

• ARMv6 memory system architecture accelerates OS context-switch

• Vectored interrupt interface and low-interrupt-latency mode speeds interrupt response and real-time performance

• Optional Vector Floating Point coprocessor (ARM1136JF-S, ARM1176JZF-S and ARM1156T2F-S cores) for automotive/industrial controls and 3D graphics acceleration

• All ARM11 cores are delivered as ARM- Synopsys Reference Methodology compliant deliverables which significantly reduce the time to generate a specific technology implementation of the core and to generate a complete set of industry standard views and models.