VHDL

VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Description Language. The United States Department of Defense develop VHDL in 1981 used to study on various Hardware Description methods and need for a standard language. The DoD made the awarded contract with a team of companies includes IBM, Texas Instruments and Intermatics. VHDL was released in 1985 and standardized as IEEE standard IEEE 1076 in 1987. In 1993 an updated standard, IEEE 1164 was adopted. In 1996 IEEE 1076.3 became a VHDL Synthesis Standard.

Why VHDL!!!!

• VHDL supports various development methods top-down, bottom-down or any mix.
• The language supports hierarchies.
• Using VHDL language it is possible to describe the behavior, function, inputs, and outputs of a digital design.
• Simulation as well as design of complex logic is possible.
• Design reuse is possible.
• VHDL provides for modular design and testing.
• Use of VHDL has tremendously reduced the “Time to Market” for large and small design.
• VHDL makes the design device independent.
• Design description can be targeted towards PLDs, FPGA or an ASIC easily.

The following naming conventions apply to VHDL designs:

• VHDL is not case sensitive.
• Two dashes “--” are used to begin comment lines.
• Names can use alphanumeric characters and the underscore “_” character.
• Names must begin with an alphabetic letter.
• You may not use two underscores in a row, or use an underscore as the last character in the name.
• Spaces are not allowed within names.
• Object names must be unique. For example, you cannot have a signal named A and a bus named A(7 downto 0).

The following is a list of the VHDL reserved keywords:

Abs	access	after	alias
all	and	architecture	array
assert	attribute	begin	block
body	buffer	bus	Case
component	configuration	constant	disconnect
downto	else	elsif	End
entity	exit	file	for
function	generate	generic	group
guarded	if	impure	in
inertial	inout	is	Label
library	linkage	literal	loop
map	mod	nand	New
next	nor	not	null
of	on	open	Or
others	out	package	port
postponed	procedure	process	Pure
range	record	register	reject
rem	report	return	Rol
ror	select	severity	shared
signal	sla	sra	srl
subtype	then	to	transport
type	unaffected	units	Until
use	variable	wait	When
while	with	xnor	xor