The ARM9 architecture follows Harvard architecture philosophy, which separates the data and instruction buses. The memory system has been redesigned, which includes a separate Data & Instruction cache and an MMU. Which results in, this processor can be used by operating systems requiring virtual memory support.
ARM9 has two variations ARM922T & ARM920T. ARM922T is a variation on the ARM920T but with half the Data + Instruction cache size. The ARM940T includes a smaller Data + Instruction cache and an MPU. The ARM940T is designed for applications that do not require a platform operating system. Both ARM920T and ARM940T execute the architecture v4T instructions.
The next processors in the ARM9 family were based on the ARM9E-S core. This core is a synthesizable version of the ARM9 core with the E extensions.
There are two variations: ARM946E-S and ARM966E-S.
Both execute architecture v5TE instructions. They also support the optional embedded trace macrocell (ETM), which allows a developer to trace instruction and data execution in real time on the processor. This is important when debugging applications with time-critical segments.
The ARM946E-S includes TCM, cache, and an MPU. The sizes of the TCM and caches are configurable. This processor is designed for use in embedded control applications that require deterministic real-time response. In contrast, the ARM966E does not have the MPU and cache extensions but does have configurable TCMs.
The latest core in the ARM9 product line is the ARM926EJ-S synthesizable processor core, announced in 2000. It is designed for use in small portable Java-enabled devices such as 3G phones and personal digital assistants (PDAs). The ARM926EJ-S is the first ARM processor core to include the Jazelle technology, which accelerates Java bytecode execution. It features an MMU, configurable TCMs, and D +I caches with zero or nonzero wait state memories.
The ARM9 family's comprehensive feature set enables developers to implement leading-edge systems, while delivering considerable savings in chip area, time-to-market, development costs and power consumption.
32-bit RISC processor with ARM® and Thumb® instruction sets
5-stage integer pipeline achieves 1.1 MIPS/MHz
Up to 300 MIPS (Dhrystone 2.1) in a typical 0.13µm process
Single 32-bit AMBA bus interface
MMU supporting Windows CE, Symbian OS, Linux, Palm OS ( and )
Integrated instruction and data caches
Excellent debug support for SoC designers, including ETM interface
8-entry write buffer — avoids stalling the processor when writes to external memory are performed
Portable to latest 0.18µm, 0.15µm, 0.13µm silicon processes.