System designers are always competing to build cost-effective products as fast as possible in a highly competitive environment. In order to achieve this, they are turning to using a top-down design methodology that includes using Hardware description languages and synthesis, in addition some just the more traditional process of simulation. A product in this instance is any electronic equipment containing Application Specific Integrated Circuits (ASICs), or Field Programmable Gate Arrays (FPGAs).
In recent years, designers have increasingly adopted top down methodologies even though it takes them away from logic and transistor level design to abstract programming. The introduction of industry standard hardware description languages and commercially available synthesis tools has helped establish this revolutionary design methodology. The advantages are clear and engineers design method must change. Some of the advantages are:
Increased productivity yields shorter development cycle with more product features and reduce time to market,
Reduce Non-Recurring Engineering (NRE) cost,
Design reuse is enabled,
Increase flexibility to design changes,
Faster exploration of alternative architectures,
Faster exploration of alternative technology libraries,
Enable use of synthesis to rapidly sweep the design space of area and timing, and to automatically generate testable circuits,
Better and easier design auditing and verification.
The final manufacturing process of connecting the transistors together is then completed when a chip designer has specific design he or she wishes to implement in the ASIC. An ASIC vendor can do this in a couple of weeks and is known as the turn-around time. There are two categories of ASIC devices; Gate Arrays and Standard Cells.
The library of cells provided by a gate array vendor will contain: primitive logic gates, registers, hard-macros and soft-macros. Hard-macros and soft-macros are usually of MSI and LSI complexity, such as multiplexers, comparators and counters.
Standard cells devices do not have any concept of basic cell and no components are prefabricated on the silicon chip. The manufacturers supply hard-macros and soft-macros library containing elements of LSI and VLSI complexity, such as controllers, ALUs and microprocessors. Additionally, soft-macros library contains RAM functions that can not be implemented efficiently in gate array devices; ROM functions are more efficiently implemented in cell primitives.
The field programmable gate array is a device that is completely manufactured, but that remains design independent. The primitive architectures in FPGA device manufactured by the FPGA vendor includes a number of programmable logic blocks that are connected to programmable switching matrices. To configure a device for a particular function operation these switches matrices are programmed to route signals between the individual logic blocks.
The Choice of ASIC or FPGA
The cost of ASIC device is cheaper than that of FPGA devices, considering the Non Recurring Engineering (NRE) cost. The advantage of FPGAs is that they are quick and easy to program. The design implemented on FPGAs for small production runs and then retargeted to an ASICs for larger production.